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(R)
X9251
Single Supply/Low Power/256-Tap/SPI Bus
Data Sheet September 14, 2005 FN8166.2
Quad Digitally-Controlled (XDCPTM) Potentiometer
FEATURES * Four potentiometers in one package * 256 resistor taps-0.4% resolution * SPI Serial Interface for write, read, and transfer operations of the potentiometer * Wiper resistance: 100 typical @ VCC = 5V * 4 Non-volatile data registers for each potentiometer * Non-volatile storage of multiple wiper positions * Standby current < 5A max * VCC: 2.7V to 5.5V Operation * 50k, 100k versions of total resistance * 100 yr. data retention * Single supply version of X9250 * Endurance: 100,000 data changes per bit per register * 24 Ld SOIC, 24 Ld TSSOP * Low power CMOS * Pb-free plus anneal available (RoHS compliant) FUNCTIONAL DIAGRAM
DESCRIPTION The X9251 integrates four digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated circuit. The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the SPI bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and four non-volatile Data Registers that can be directly written to and read by the user. The content of the WCR controls the position of the wiper. At power-up, the device recalls the content of the default Data Registers of each DCP (DR00, DR10, DR20, and DR30) to the corresponding WCR. The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing.
VCC
RH0
RH1
RH2
RH3
HOLD A1 A0 SO SI SCK CS SPI Interface WCR0 DR00 DR01 DR02 DR03
DCP0
POWER UP, INTERFACE CONTROL AND STATUS
WCR1 DR10 DR11 DR12 DR13
DCP1
WCR2 DR20 DR21 DR22 DR23
DCP2
WCR3 DR30 DR31 DR32 DR33
DCP3
VSS
WP
RW0
RL0
RW1
RL1
RW2
RL2
RW3
RL3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
X9251 Ordering Information
PART NUMBER X9251UP24I X9251US24* X9251US24Z* (Note) X9251US24I* X9251US24IZ* (Note) X9251UV24 X9251UV24Z (Note) X9251UV24I X9251UV24IZ (Note) X9251TP24I X9251TS24* X9251TS24Z* (Note) X9251TS24I* X9251TS24IZ* (Note) X9251TV24 X9251TV24Z (Note) X9251TV24I X9251TV24IZ (Note) X9251US24-2.7* X9251US24Z-2.7* (Note) X9251US24I-2.7* X9251US24IZ-2.7* (Note) X9251UV24-2.7 X9251UV24Z-2.7 (Note) X9251UV24I-2.7 X9251UV24IZ-2.7 (Note) X9251TS24-2.7* X9251TS24Z-2.7* (Note) X9251TS24I-2.7* X9251TS24IZ-2.7* (Note) X9251TV24-2.7 X9251TV24Z-2.7 (Note) X9251TV24I-2.7 X9251TV24IZ-2.7 (Note) X9251TS X9251TS Z X9251TS I X9251TS Z I X9251TV X9251TV Z X9251TV I X9251TV Z I X9251US F X9251US Z F X9251US G X9251US Z G X9251UV F X9251UV Z F X9251UV G X9251UV Z G X9251TS F X9251TS Z F X9251TS G X9251TS Z G X9251TV F X9251TV Z F X9251TV G X9251TV Z G 100 2.7 to 5.5 50 PART MARKING X9251UP I X9251US X9251US Z X9251US I X9251US Z I X9251UV X9251UV Z X9251UV I X9251UV Z I 100 VCC LIMITS (V) 5 10% POTENTIOMENTER TEMP RANGE ORGANIZATION (k) (C) 50 -40 to +85 0 to 70 0 to 70 -40 to +85 -40 to +85 0 to 70 0 to 70 -40 to +85 -40 to +85 -40 to +85 0 to 70 0 to 70 -40 to +85 -40 to +85 0 to 70 0 to 70 -40 to +85 -40 to +85 0 to 70 0 to 70 -40 to +85 -40 to +85 0 to 70 0 to 70 -40 to +85 -40 to +85 0 to 70 0 to 70 -40 to +85 -40 to +85 0 to 70 0 to 70 -40 to +85 -40 to +85 24 Ld PDIP 24 Ld SOIC (300MIL) 24 Ld SOIC (300MIL) (Pb-Free) 24 Ld SOIC (300MIL) 24 Ld SOIC (300MIL) (Pb-Free) 24 Ld TSSOP (4.4mm) 24 Ld TSSOP (4.4mm) (Pb-free) 24 Ld TSSOP (4.4mm) 24 Ld TSSOP (4.4mm) (Pb-free) 24 Ld PDIP 24 Ld SOIC (300MIL) 24 Ld SOIC (300MIL) (Pb-Free) 24 Ld SOIC (300MIL) 24 Ld SOIC (300MIL) (Pb-Free) 24 Ld TSSOP (4.4mm) 24 Ld TSSOP (4.4mm) (Pb-free) 24 Ld TSSOP (4.4mm) 24 Ld TSSOP (4.4mm) (Pb-free) 24 Ld SOIC (300MIL) 24 Ld SOIC (300MIL) (Pb-Free) 24 Ld SOIC (300MIL) 24 Ld SOIC (300MIL) (Pb-Free) 24 Ld TSSOP (4.4mm) 24 Ld TSSOP (4.4mm) (Pb-free) 24 Ld TSSOP (4.4mm) 24 Ld TSSOP (4.4mm) (Pb-free) 24 Ld SOIC (300MIL) 24 Ld SOIC (300MIL) (Pb-Free) 24 Ld SOIC (300MIL) 24 Ld SOIC (300MIL) (Pb-Free) 24 Ld TSSOP (4.4mm) 24 Ld TSSOP (4.4mm) (Pb-free) 24 Ld TSSOP (4.4mm) 24 Ld TSSOP (4.4mm) (Pb-free) PACKAGE
*Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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CIRCUIT LEVEL APPLICATIONS * Vary the gain of a voltage amplifier * Provide programmable dc reference voltages for comparators and detectors * Control the volume in audio circuits * Trim out the offset voltage error in a voltage amplifier circuit * Set the output voltage of a voltage regulator * Trim the resistance in Wheatstone bridge circuits * Control the gain, characteristic frequency and Q-factor in filter circuits * Set the scale factor and zero point in sensor signal conditioning circuits * Vary the frequency and duty cycle of timer ICs * Vary the dc biasing of a pin diode attenuator in RF circuits * Provide a control variable (I, V, or R) in feedback circuits SYSTEM LEVEL APPLICATIONS * Adjust the contrast in LCD displays * Control the power level of LED transmitters in communication systems * Set and regulate the DC biasing point in an RF power amplifier in wireless systems * Control the gain in audio and home entertainment systems * Provide the variable DC bias for tuners in RF wireless systems * Set the operating points in temperature control systems * Control the operating point for sensors in industrial systems * Trim offset and gain errors in artificial intelligent systems PIN ASSIGNMENTS
Pin (SOIC) 1 2 3 4 5 7 8 9 10 11 12 13 14 15 16 17 18 20 21 22 23 24 6, 19 Symbol SO A0 RW3 RH3 RL3 VCC RL0 RH0 RW0 CS WP SI A1 RL1 RH1 RW1 VSS RW2 RH2 RL2 SCK HOLD NC Function Serial Data Output for SPI bus Device Address for SPI bus. (See Note 1) Wiper Terminal of DCP3 High Terminal of DCP3 Low Terminal of DCP3 System Supply Voltage Low Terminal of DCP0 High Terminal of DCP0 Wiper Terminal of DCP0 SPI bus. Chip Select active low input Hardware Write Protect - active low Serial Data Input for SPI bus Device Address for SPI bus. (See Note 1) Low Terminal of DCP1 High Terminal of DCP1 Wiper Terminal of DCP1 System Ground Wiper Terminal of DCP2 High Terminal of DCP2 Low Terminal of DCP2 Serial Clock for SPI bus Device select. Pauses the SPI serial bus. No Connect SO A0 RW3 RH3 RL3 NC VCC RL0 RH0 RW0 CS WP
PIN CONFIGURATION
SOIC/TSSOP 1 2 3 4 5 6 7 8 9 10 11 12 X9251 24 23 22 21 20 19 18 17 16 15 14 13 HOLD SCK RL2 RH2 RW2 NC VSS RW1 RH1 RL1 A1 SI
Note 1: A0 - A1 device address pins must be tied to a logic level.
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PIN DESCRIPTIONS Bus Interface Pins SERIAL OUTPUT (SO) SO is a serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. SERIAL INPUT (SI) SI is the serial data input pin. All opcodes, byte addresses and data to be written to the device registers are input on this pin. Data is latched by the rising edge of the serial clock. SERIAL CLOCK (SCK) The SCK input is used to clock data into and out of the X9251. HOLD (HOLD) HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times. DEVICE ADDRESS (A1 - A0) The address inputs are used to set the two least significant bits of the slave address. A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9251. Device pins A1 - A0 must be tie to a logic level which specify the internal address of the device, see Figures 2, 3, 4, 5 and 6. CHIP SELECT (CS) When CS is HIGH, the X9251 is deselected and the SO pin is at high impedance, and (unless an internal write cycle is underway) the device is in the standby state. CS LOW enables the X9251, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Potentiometer Pins RH, RL The RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. Since there are 4 potentiometers, there are 4 sets of RH and RL such that RH0 and RL0 are the terminals of DCP0 and so on. RW The wiper pin are equivalent to the wiper terminal of a mechanical potentiometer. Since there are 4 potentiometers, there are 4 sets of RW such that RW0 is the terminals of DCP0 and so on. Supply Pins SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (VSS) The VCC pin is the system supply voltage. The VSS pin is the system ground. Other Pins NO CONNECT No connect pins should be left floating. This pins are used for Intersil manufacturing and testing purposes. HARDWARE WRITE PROTECT INPUT (WP) The WP pin when LOW prevents non-volatile writes to the Data Registers. PRINCIPLES OF OPERATION The X9251 is an integrated circuit incorporating four DCPs and their associated registers and counters, and a serial interface providing direct communication between a host and the potentiometers. DCP Description Each DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL pins). The RW pin is an intermediate node, equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by an 8-bit volatile Wiper Counter Register (WCR).
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Figure 1. Detailed Potentiometer Block Diagram One of Four Potentiometers
#: 0, 1, 2, or 3 SERIAL DATA PATH FROM INTERFACE CIRCUITRY DR#0 8 DR#1 8 PARALLEL BUS INPUT WIPER COUNTER REGISTER (WCR#) SERIAL BUS INPUT RH
DR#2
DR#3
COUNTER --DECODE
DCP CORE
RW
IF WCR = 00[H] then RW is closet to RL IF WCR = FF[H] then RW is closet to RH
INC/DEC LOGIC UP/DN MODIFIED SCK UP/DN CLK RL
Power Up and Down Recommendations. There are no restrictions on the power-up or powerdown conditions of VCC and the voltages applied to the potentiometer pins provided that VCC is always more positive than or equal to VH, VL, and VW, i.e., VCC VH, VL, VW. The VCC ramp rate specification is always in effect. Wiper Counter Register (WCR) The X9251 contains four Wiper Counter Registers, one for each potentiometer. The Wiper Counter Register can be envisioned as a 8-bit parallel and serial load counter with its outputs decoded to select one of 256 wiper positions along its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the Write Wiper Counter Register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data registers via the XFR Data Register instruction (parallel load); it can be modified one step at a time by the Increment/Decrement instruction (See Instruction section for more details). Finally, it is loaded with the contents of its Data Register zero (DR#0) upon power-up. (See Figure 1.) The wiper counter register is a volatile register; that is, its contents are lost when the X9251 is powered-down. Although the register is automatically loaded with the value in DR#0 upon power-up, this may be different
from the value present at power-down. Power-up guidelines are recommended to ensure proper loadings of the DR#0 value into the WCR#. Data Registers (DR) Each of the four DCPs has four 8-bit non-volatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the four Data Registers and the associated Wiper Counter Register. All operations changing data in one of the Data Registers is a non-volatile operation and takes a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as regular memory locations for system parameters or user preference data. Bits [7:0] are used to store one of the 256 wiper positions or data (0~255). Status Register (SR) This 1-bit Status Register is used to store the system status. WIP: Write In Progress status bit, read only. - When WIP=1, indicates that high-voltage write cycle is in progress. - When WIP=0, indicates that no high-voltage write cycle is in progress.
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Table 1. Wiper counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile).
WCR7 (MSB) WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0 (LSB)
Table 2. Data Register, DR (8-bit), DR[7:0]: Used to store wiper positions or data (Non-volatile).
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
SERIAL INTERFACE The X9251 supports the SPI interface hardware conventions. The device is accessed via the SI input with data clocked in, on the rising SCK. CS must be LOW and the HOLD and WP pins must be HIGH during the entire operation. The SO and SI pins can be connected together, since they have three state outputs. This can help to reduce system pin count. IDENTIFICATION BYTE The first byte sent to the X9251 from the host, following a CS going HIGH to LOW, is called the Identification Byte. The most significant four bits of the Identification Byte are a Device Type Identifier, ID[3:0]. For the X9251, this is fixed as 0101 (refer to Table 3). Table 3. Identification Byte Format
Device Type Identifier
The least significant four bits of the Identification Byte are the Slave Address bits, AD[3:0]. For the X9251, A3 is 0, A2 is 0, A1 is the logic value at the input pin A1, and A0 is the logic value at the input pin A0. Only the device which Slave Address matches the incoming bits sent by the master executes the instruction. The A1 and A0 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. INSTRUCTION BYTE The next byte sent to the X9251 contains the instruction and register pointer information. The four most significant bits are used provide the instruction opcode (I[3:0]). The RB and RA bits point to one of the four Data Registers of each associated XDCP. The least two significant bits point to one of four Wiper Counter Registers or DCPs.The format is shown below in Table 4.
Slave Address
ID3 0 (MSB)
ID2 1
ID1 0
ID0 1
A3 0
A2 0
A1 Pin A1 Logic Value
A0 Pin A0 Logic Value (LSB)
Table 4. Instruction Byte Format
Instruction Opcode Register Selection DCP Selection (WCR Selection)
I3 (MSB)
I2
I1
I0
RB
RA
P1
P0 (LSB)
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Data Register Selection Register
DR#0 DR#1 DR#2 DR#3
RB
0 0 1 1
RA
0 1 0 1
#: 0, 1, 2, or 3 Table 5. Instruction Set Instruction
Read Wiper Counter Register Write Wiper Counter Register Read Data Register Write Data Register XFR Data Register to Wiper Counter Register XFR Wiper Counter Register to Data Register Global XFR Data Registers to Wiper Counter Registers Global XFR Wiper Counter Registers to Data Register Increment/Decrement Wiper Counter Register
Note: 1/0 = data is one or zero
I3 1
1 1 1 1
I2 0
0 0 1 1
Instruction Set I1 I0 RB RA 0 1 0 0
1 1 0 0 0 1 0 1 0 1/0 1/0 1/0 0 1/0 1/0 1/0
P1
1/0 1/0 1/0 1/0 1/0
P0
1/0 1/0 1/0 1/0 1/0
Operation
Read the contents of the Wiper Counter Register pointed to by P1 - P0 Write new value to the Wiper Counter Register pointed to by P1 - P0 Read the contents of the Data Register pointed to by P1 - P0 and RB - RA Write new value to the Data Register pointed to by P1 - P0 and RB - RA Transfer the contents of the Data Register pointed to by P1 - P0 and RB - RA to its associated Wiper Counter Register Transfer the contents of the Wiper Counter Register pointed to by P1 - P0 to the Data Register pointed to by RB - RA Transfer the contents of the Data Registers pointed to by RB - RA of all four pots to their respective Wiper Counter Registers Transfer the contents of both Wiper Counter Registers to their respective data Registers pointed to by RB - RA of all four pots Enable Increment/decrement of the Control Latch pointed to by P1 - P0
1
1
1
0
1/0
1/0
1/0
1/0
0
0
0
1
1/0
1/0
0
0
1
0
0
0
1/0
1/0
0
0
0
0
1
0
0
0
1/0
1/0
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Instructions Four of the nine instructions are three bytes in length. These instructions are: - Read Wiper Counter Register - read the current wiper position of the selected potentiometer, - Write Wiper Counter Register - change current wiper position of the selected potentiometer, - Read Data Register - read the contents of the selected Data Register, - Write Data Register - write a new value to the selected Data Register, - Read Status - this command returns the contents of the WIP bit which indicates if the internal write cycle is in progress. The basic sequence of the three byte instructions is illustrated in Figure 3. These three-byte instructions exchange data between the WCR and one of the Data Registers. A transfer from a Data Register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action is delayed by tWRL. A transfer from the WCR (current wiper position), to a Data Register is a write to non-volatile memory and takes a minimum of tWR to complete. The transfer can occur between one of the four potentiometer's WCR, and one of its associated registers, DRs; or it may occur globally, where the transfer occurs between all potentiometers and one associated register. The Read Status Register instruction is the only unique format (See Figure 5). Four instructions require a two-byte sequence to complete. These instructions transfer data between the host and the X9251; either between the host and one of the data registers or directly between the host and the Wiper Counter Register. These instructions are: - XFR Data Register to Wiper Counter Register - This transfers the contents of one specified Data Register to the associated Wiper Counter Register. - XFR Wiper Counter Register to Data Register - This transfers the contents of the specified Wiper Counter Register to the specified associated Data Register. - Global XFR Data Register to Wiper Counter Register - This transfers the contents of all specified Data Registers to the associated Wiper Counter Registers. - Global XFR Wiper Counter Register to Data Register - This transfers the contents of all Wiper Counter Registers to the specified associated Data Registers. INCREMENT/DECREMENT COMMAND The final command is Increment/Decrement (See Figures 6 and 7). The Increment/Decrement command is different from the other commands. Once the command is issued and the X9251 has responded with an Acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine tuning capability to the host. For each SCK clock pulse (tHIGH) while SI is HIGH, the selected wiper moves one wiper position towards the RH terminal. Similarly, for each SCK clock pulse while SI is LOW, the selected wiper moves one wiper position towards the RL terminal. A detailed illustration of the sequence and timing for this operation are shown. See Instruction format for more details.
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Figure 2. Two-Byte Instruction Sequence
CS SCK
SI
0
1
0
1
0 0
0 0 A1 A0 I3 I2 I1 I0 RB RA P1 P0
ID3 ID2 ID1 ID0 Device ID
Internal Address
Instruction Opcode
Register DCP/WCR Address Address
Figure 3. Three-Byte Instruction Sequence SPI Interface; Write Case
CS SCK SI 0 0 0 0 A1 A0 Internal Address I3 I2 I1 I0 RB RA P1 P0 Register DCP/WCR Address Address D7 D6 D5 D4 D3 D2 D1 D0 Data for WCR[7:0] or DR[7:0]
0
1
0
1
ID3 ID2 ID1 ID0 Device ID
Instruction Opcode
Figure 4. Three-Byte Instruction Sequence SPI Interface, Read Case
CS SCK SI 0 0 0 0 A1 A0 Internal Address I3 I2 I1 I0 RB RA P1 P0 Register DCP/WCR Address Address
0
1
0
1
X
X
X
X
X
X
X
X
ID3 ID2 ID1 ID0 Device ID
Don't Care
Instruction Opcode
S0 D7 D6 D5 D4 D3 D2 D1 D0 WCR[7:0] or Data Register Bit [7:0]
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Figure 5. Three-Byte Instruction Sequence (Read Status Register
CS SCK SI
0
1
0
1
0 0
0 0 A1 A0 Internal Address
1 I3
0 I2
1
1 RB RA P1 P0 Register Pot/WCR Address Address
0
0
0
0
0
0
0 WIP Status Bit
ID3 ID2 ID1 ID0 Device ID
I1 I0
Instruction Opcode
Figure 6. Increment/Decrement Instruction Sequence
CS SCK SI 0 0 0 0 A1 A0 Internal Address I2 I3 I1 I0 RB RA P1 P0 Register Pot/WCR Address Address I N C 1 I N C 2 I N C n D E C 1 D E C n
0
1
0
1
ID3 ID2 ID1 ID0 Device ID
Instruction Opcode
Figure 7. Increment/Decrement Timing Spec
tWRID SCK
SI
R W
VOLTAGE OUT
INC/DEC CMD ISSUED
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INSTRUCTION FORMAT Read Wiper Counter Register (WCR)
Device Type Identifier 0 1 0 1 Device Addresses Instruction Opcode 0 0 1 WCR Addresses 0 0 0 Wiper Position (Sent by X9251 on SO) W C R 6 W C R 5 W C R 4 W C R 3 W C R 2 W C R 1
CS Falling Edge
0 0 A1 A0 1
W C 0 R 7
CS W Rising C Edge R 0
Write Wiper Counter Register (WCR)
Device Type Identifier 1 0 1 Device Addresses Instruction Opcode 0 1 0 WCR Addresses 0 0 0 W C 0 R 7 Data Byte (Sent by Host on SI) W C R 6 W C R 5 W C R 4 W C R 3 W C R 2 W C R 1
CS Falling Edge 0
0 0 A1 A0 1
CS W Rising C Edge R 0
Read Data Register (DR)
Device Type Device Instruction DR and WCR Data Byte CS CS Identifier Addresses Opcode Addresses (Sent by X9271 on SO) Falling Rising Edge 0 1 0 1 0 0 A1 A0 1 0 1 1 RB RA P1 P0 D D D D D D D D Edge 76543210
Write Data Register (DR)
HIGH-VOLTAGE WRITE CYCLE
FN8166.2 September 14, 2005
CS CS Falling Rising Edge 0 1 0 1 0 0 A1 A0 1 1 0 0 RB RA P1 P0 D D D D D D D D Edge 76543210
Device Type Identifier
Device Addresses
Instruction Opcode
DR and WCR Addresses
Data Byte (Sent by Host on SI)
Global Transfer Data Register (DR) to Wiper Counter Register (WCR)
Device Type CS Identifier Falling Edge 0 1 0 1 Device Addresses 0 CS Rising 0 A1 A0 0 0 0 1 RB RA 0 0 Edge Instruction Opcode DR Addresses
Notes: (1) (2) (2) (3)
"A1 ~ A0": stands for the device addresses sent by the master. WPx refers to wiper position data in the Counter Register "I": stands for the increment operation, SI held HIGH during active SCK phase (high). "D": stands for the decrement operation, SI held LOW during active SCK phase (high).
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X9251
Global Transfer Wiper Counter Register (WCR) to Data Register (DR)
Device Type Device Instruction DR CS CS Identifier Addresses Opcode Addresses Falling Rising Edge 0 1 0 1 0 0 A1 A0 1 0 0 0 RB RA 0 0 Edge HIGH-VOLTAGE WRITE CYCLE
Transfer Wiper Counter Register (WCR) to Data Register (DR)
Device Type Device Instruction DR and WCR CS Identifier Addresses Opcode Addresses Falling Edge 0 1 0 1 0 0 A1 A0 1 1 1 0 RB RA 0 0 CS Rising Edge HIGH-VOLTAGE WRITE CYCLE
Transfer Data Register (DR) to Wiper Counter Register (WCR)
Device Type Device Instruction DR and WCR CS Identifier Addresses Opcode Addresses Falling Edge 0 1 0 1 0 0 A1 A0 1 1 0 1 RB RA 0 0 CS Rising Edge
Increment/Decrement Wiper Counter Register (WCR)
Device Type Device Instruction WCR Increment/Decrement CS CS Identifier Addresses Opcode Addresses (Sent by Master on SI) Falling Rising Edge 0 1 0 1 0 0 A1 A0 0 0 1 0 X X 0 0 I/D I/D . . . . I/D I/D Edge
Read Status Register (SR)
Device Type Device Instruction WCR Data Byte CS Identifier Addresses Opcode Addresses (Sent by X9251 on SO) Falling Edge 0 1 0 1 0 0 A1 A0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 WIP CS Rising Edge
Notes: (1) (2) (2) (3)
"A1 ~ A0": stands for the device addresses sent by the master. WPx refers to wiper position data in the Counter Register "I": stands for the increment operation, SI held HIGH during active SCK phase (high). "D": stands for the decrement operation, SI held LOW during active SCK phase (high).
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ABSOLUTE MAXIMUM RATINGS Temperature under bias .................... -65C to +135C Storage temperature ......................... -65C to +150C Voltage on SCK, any address input, VCC with respect to VSS ................................. -1V to +7V V = | (VH - VL) |................................................... 5.5V Lead temperature (soldering, 10s) .................... 300C IW (10s) ..............................................................6mA COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS Temp Commercial Industrial Min. 0C -40C Max. +70C +85C Device X9251 X9251-2.7 Supply Voltage (VCC) Limits(4) 5V 10% 2.7V to 5.5V
ANALOG CHARACTERISTICS (Over recommended industrial operating conditions unless otherwise stated.) Parameter Symbol
RTOTAL RTOTAL End to End Resistance End to End Resistance End to End Resistance Tolerance Power Rating IW RW Wiper Current Wiper Resistance
Limits Min. Typ.
100 50 20 50 3 300 150
Max.
Units
k k % mW mA V % IW = IW =
Test Conditions
T version U version 25C, each pot V(VCC) @ VCC = 3V RTOTAL V(VCC) @ VCC = 5V RTOTAL
VTERM
Voltage on any RH or RL Pin Noise Resolution Absolute Linearity (1) Relative Linearity (2) Temperature Coefficient of RTOTAL Ratiometric Temp. Coefficient
VSS -120 0.4 -1 -0.6 300 -20 10/10/25
VCC
VSS = 0V
dBV/Hz Ref: 1V +1 +0.6 MI(3) MI(3) ppm/C +20 ppm/C pF See Macro model Rw(n)(actual) - Rw(n)(expected)(5) Rw(n + 1) - [Rw(n) + MI](5)
CH/CL/CW
Potentiometer Capacitances
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (3) MI = RTOT / 255 or (RH - RL) / 255, single pot (4) During power up VCC > VH, VL, and VW. (5) n = 0, 1, 2, ...,255; m =0, 1, 2, ..., 254.
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D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Limits Symbol
ICC1 ICC2 ISB ILI ILO VIH VIL VOL VOH VOH
Parameter
VCC supply current (active) VCC supply current (non-volatile write) VCC current (standby) Input leakage current Output leakage current Input HIGH voltage Input LOW voltage Output LOW voltage Output HIGH voltage Output HIGH voltage
Min.
Typ.
Max.
400
Units
A mA A A A V V V V V IOL = 3mA
Test Conditions
fSCK = 2.5 MHz, SO = Open, VCC = 6V Other Inputs = VSS fSCK = 2.5MHz, SO = Open, VCC = 6V Other Inputs = VSS SCK = SI = VSS, Addr. = VSS, CS = VCC = 6V VIN = VSS to VCC VOUT = VSS to VCC
1
5 3 10 10
VCC x 0.7 -1 VCC - 0.8 VCC - 0.4
VCC + 1 VCC x 0.3 0.4
IOH = -1mA, VCC +3V IOH = -0.4mA, VCC +3V
ENDURANCE AND DATA RETENTION Parameter
Minimum endurance Data retention
Min.
100,000 100
Units
Data changes per bit per register years
CAPACITANCE Symbol
CIN/OUT
) (6
Test
Input / Output capacitance (SI) Output capacitance (SO) Input capacitance (A0, A1, CS, WP, HOLD, and SCK)
Max.
8 8 6
Units
pF pF pF
Test Conditions
VOUT = 0V VOUT = 0V VIN = 0V
COUT(6) CIN(6)
POWER-UP TIMING Symbol
tr VCC
(6)
Parameter
VCC Power-up rate Power-up to initiation of read operation Power-up to initiation of write operation
Min.
0.2
Max.
50 1 50
Units
V/ms ms ms
tPUR(7) tPUW(7)
A.C. TEST CONDITIONS Input Pulse Levels
Input rise and fall times Input and output timing level VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5
Notes: (6) This parameter is not 100% tested (7) tPUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 100% tested.
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FN8166.2 September 14, 2005
X9251
EQUIVALENT A.C. LOAD CIRCUIT
VCC 2k RH SO pin 2k 10pF 10pF RW CL CW 25pF CL 10pF SPICE Macromodel RTOTAL RL
AC TIMING Symbol
fSCK tCYC tWH tWL tLEAD tLAG tSU tH tRI tFI tDIS tV tHO tRO tFO tHOLD tHSU tHH tHZ tLZ TI tCS tWPASU tWPAH SPI clock frequency SPI clock cycle rime SPI clock high rime SPI clock low time Lead time Lag time SI, SCK, HOLD and CS input setup time SI, SCK, HOLD and CS input hold time SI, SCK, HOLD and CS input rise time SI, SCK, HOLD and CS input fall time SO output disable time SO output valid time SO output hold time SO output rise time SO output fall time HOLD time HOLD setup time HOLD hold time HOLD low to output in high Z HOLD high to output in low Z Noise suppression time constant at SI, SCK, HOLD and CS inputs CS deselect time WP, A0 setup time WP, A0 hold time 2 0 0 400 100 100 100 100 10 0 100 100 0 500 200 200 250 250 50 50 2 2 250 200
Parameter
Min.
Max.
2
Units
MHz ns ns ns ns ns ns ns s s ns ns ns ns ns ns ns ns ns ns ns s ns ns
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FN8166.2 September 14, 2005
X9251
HIGH-VOLTAGE WRITE CYCLE TIMING Symbol
tWR
Parameter
High-voltage write cycle time (store instructions)
Typ.
5
Max.
10
Units
ms
XDCP TIMING Symbol
tWRPO tWRL
Parameter
Wiper response time after the third (last) power supply is stable Wiper response time after instruction issued (all load instructions)
Min.
5 5
Max. Units
10 10 s s
SYMBOL TABLE
WAVEFORM INPUTS Must be steady May change from Low to High May change from High to Low Don't Care: Changes Allowed N/A OUTPUTS Will be steady Will change from Low to High Will change from High to Low Changing: State Not Known Center Line is High Impedance
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X9251
TIMING DIAGRAMS Input Timing
tCS CS tLEAD SCK tSU SI MSB tH tWL tCYC ... tWH ... tLAG
tFI LSB
tRI
SO
High Impedance
Output Timing
CS
SCK tV SO MSB tHO
... tDIS ... LSB
SI
ADDR
Hold Timing
CS tHSU SCK tRO SO tHZ SI tHOLD HOLD tLZ tFO tHH ...
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FN8166.2 September 14, 2005
X9251
XDCP Timing (for All Load Instructions)
CS
SCK
... tWRL MSB ... LSB
SI
VWx
SO
High Impedance
Write Protect and Device Address Pins Timing
(Any Instruction) tWPASU WP A0 A1 tWPAH
CS
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FN8166.2 September 14, 2005
X9251
APPLICATIONS INFORMATION Basic Configurations of Electronic Potentiometers
VR +VR
RW
I Three terminal Potentiometer; Variable voltage divider
Two terminal Variable Resistor; Variable current
Application Circuits Noninverting Amplifier
VS + - VO VIN 317 R1 R2 R1 VO (REG)
Voltage Regulator
Iadj R2
VO = (1+R2/R1)VS
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
Offset Voltage Adjustment
R1 VS 100k - + TL072 10k 10k +12V 10k -12V VO R2
Comparator with Hysterisis
VS - + VO
VUL = {R1/(R1+R2)} VO(max) RLL = {R1/(R1+R2)} VO(min)
} R1
} R2
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FN8166.2 September 14, 2005
X9251
Application Circuits (continued) Attenuator
C VS R1 - VS R3 R4 R1 = R2 = R3 = R4 = 10k R1 + VO R2 R + - VO
Filter
R2
V O = G VS -1/2 G +1/2
GO = 1 + R2/R1 fc = 1/(2RC)
Inverting Amplifier
R1 R2
Equivalent L-R Circuit
}
VS
}
- + VO
C1 VS
R2 + -
V O = G VS G = - R2/R1
ZIN
R1 R3
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2
Function Generator
C
- +
R2
R1 - +
} RA } RB
frequency R1, R2, C amplitude RA, RB
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FN8166.2 September 14, 2005
X9251
PACKAGING INFORMATION 24-Lead Plastic, TSSOP, Package Code V24
.026 (.65) BSC
.169 (4.3) .252 (6.4) BSC .177 (4.5)
.303 (7.70) .311 (7.90)
.047 (1.20) .0075 (.19) .0118 (.30)
.002 (.06) .005 (.15)
.010 (.25) Gage Plane 0 - 8 .020 (.50) .030 (.75) Detail A (20X) (0.42) (0.65) .031 (.80) .041 (1.05) See Detail "A" ALL MEASUREMENTS ARE TYPICAL Seating Plane (1.78) (4.16) (7.72)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
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FN8166.2 September 14, 2005
X9251
PACKAGING INFORMATION 24-Lead Plastic, SOIC, Package Code S24
0.290 (7.37) 0.393 (10.00) 0.299 (7.60) 0.420 (10.65) Pin 1 Index Pin 1
0.014 (0.35) 0.020 (0.50) 0.598 (15.20) 0.610 (15.49) (4X) 7
0.092 (2.35) 0.105 (2.65) 0.003 (0.10) 0.012 (0.30)
0.050 (1.27)
0.050" Typical 0.010 (0.25) X 45 0.020 (0.50) 0.050" Typical 0.009 (0.22) 0.013 (0.33) 0.015 (0.40) 0.050 (1.27) 0.420"
0 - 8
FOOTPRINT
0.030" Typical 24 Places
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 22
FN8166.2 September 14, 2005

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